Method for via formation by micro-imprinting

ABSTRACT

A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of co-pending U.S. patent applicationSer. No. 16/192,546, filed Nov. 15, 2018, which is herein incorporatedby reference in its entirety.

BACKGROUND Field

Embodiments of the present disclosure generally relate to methods ofmicro-imprinting panels for advanced packaging applications.

Description of the Related Art

As circuit densities increase and device sizes decrease for nextgeneration semiconductor devices, providing the external connections,i.e., wiring, to these devices requires advanced packaging technologies.One such packaging technology is wafer level packaging.

Wafer level packaging streamlines the manufacturing and packagingprocesses of semiconductor devices by integrating device manufacturing,package assembly (packaging), electrical testing, and reliabilitytesting (burn-in) at the wafer level, where forming of the top andbottom layers of the packaging, creating the I/O connections, andtesting the packaged device are all performed before the devices aresingulated into individual packaged components. The advantages of waferlevel packaging include reduced overall manufacturing costs of theresulting device, reduced package size, and improved electrical andthermal performance.

Wafer level packaging generally comprises depositing a redistributionlayer on a substrate layer, and forming a plurality of vias in theredistribution layer using lithography processes. Using conventionallithography process to form the plurality of vias can be expensive,waste material, lack resolution beyond 7 μm in advanced node highdensity redistribution layers, and be very sensitive to surfacetopologies. Additionally, the redistribution layers are typicallydeposited using conventional photolithography and etch processes whichare costly, equipment intensive, and time consuming. Using these methodsto deposit and pattern the redistribution layer may result in asignificant amount of excess material being wasted, and may makecontrolling the size and depth of the vias difficult to control.

Accordingly, there is a need in the art for improved methods ofdepositing and forming vias in redistribution layers in wafer levelpackaging schemes.

SUMMARY

The present disclosure generally relates to methods of forming aplurality of vias in panels for advanced packaging applications. Aredistribution layer is deposited on a substrate layer. Theredistribution layer may be deposited using a spin coating process, aspray coating process, a drop coating process, or lamination. Theredistribution layer is then micro-imprinted using a stamp inside achamber. The redistribution layer and the stamp are then baked insidethe chamber. The stamp is removed from the redistribution layer to forma plurality of vias in the redistribution layer. Excess residue built-upon the redistribution layer may be removed using a descumming process. Aresidual thickness layer disposed between the bottom of each of theplurality of vias and the top of the substrate layer may have thicknessof less than about 1 μm.

In one embodiment, a method of forming a plurality of vias in a panelcomprises depositing a polyimide layer on a substrate layer,micro-imprinting the polyimide layer with a stamp inside a chamber,baking the polyimide layer and the stamp inside the chamber, exposingthe polyimide layer and the stamp to UV light, removing the stamp fromthe polyimide layer to form a plurality of vias in the polyimide layer,performing an oven curing process on the polyimide layer, and descummingthe polyimide layer to remove excess residue.

In another embodiment, a method of forming a plurality of vias in apanel comprises micro-imprinting a flowable epoxy layer with a stampinside a chamber, the flowable epoxy layer comprising silica particlefillers, baking the flowable epoxy layer and the stamp inside thechamber, and removing the stamp from the flowable epoxy layer to form aplurality of vias in the flowable epoxy layer.

In yet another embodiment, a method of forming a plurality of vias in apanel comprises depositing a polyimide layer on a substrate layer usinga drop coat process, micro-imprinting the polyimide layer with a stampinside a chamber, baking the polyimide layer and the stamp inside thechamber, exposing the polyimide layer and the stamp to UV light,removing the stamp from the polyimide layer to form a plurality of viasin the polyimide layer, and performing an oven curing process on thepolyimide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlyexemplary embodiments and are therefore not to be considered limiting ofits scope, may admit to other equally effective embodiments.

FIG. 1A-1I illustrate various stages of micro-imprinting a layer on asubstrate to form a plurality of vias, according to one embodiment.

FIG. 2 illustrates a method of micro-imprinting a layer on a substrateto form a plurality of vias, according to one embodiment.

FIGS. 3A-3B illustrate micro-imprinting stamps, according to variousembodiments.

FIGS. 4A-4B illustrate the in-chamber bake reducing and controlling theRTL of a polyimide layer, according to one embodiment.

FIG. 5A illustrates a substrate utilizing a flowable epoxy layer as theRDL being micro-imprinted by a stamp, according to one embodiment.

FIG. 5B illustrates a graph of time versus temperature formicro-imprinting a flowable epoxy layer, according to anotherembodiment.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

DETAILED DESCRIPTION

A method and apparatus for forming a plurality of vias in panels foradvanced packaging applications is disclosed, according to oneembodiment. A redistribution layer is deposited on a substrate layer.The redistribution layer may be deposited using a spin coating process,a spray coating process, a drop coating process, or lamination. Theredistribution layer is then micro-imprinted using a stamp inside achamber. The redistribution layer and the stamp are then baked insidethe chamber. The stamp is removed from the redistribution layer to forma plurality of vias in the redistribution layer. Excess residue built-upon the redistribution layer may be removed using a descumming process. Aresidual thickness layer disposed between the bottom of each of theplurality of vias and the top of the substrate layer may have thicknessof less than about 1 μm.

FIG. 1A-1I illustrate various stages of micro-imprinting aredistribution layer 104 on a substrate 100 to form a plurality of vias118. FIG. 2 illustrates a method of micro-imprinting a layer on asubstrate to form a plurality of vias, according to one embodiment.While FIGS. 1A-1I are shown in in a particular sequence, it is alsocontemplated that the various stages of method 200 depicted in FIGS.1A-1A can be performed in any suitable order. To facilitate a clearerunderstanding of the method 200, the method 200 of FIG. 2 will bedescribed and demonstrated using the various views of the substrate 100of FIGS. 1A-1I. While the method 200 is described using FIGS. 1A-1I,other operations not shown in FIGS. 1A-1I may be included.

FIG. 1A illustrates a substrate 100, or a portion of a panel or wafer,having a redistribution layer (RDL) 104 being deposited on a substratelayer 102 in a chamber 106, as performed in operation 202 of method 200of FIG. 2. The RDL 104 may be a dielectric layer. In one embodiment, theRDL 104 is pre-baked in the chamber 106 at a temperature between about75-90 degrees Celsius for about 30-45 seconds, such as 30 seconds. TheRDL 104 is deposited to have a thickness 110 between about 5 μm to 15μm. The thickness 110 of the RDL 104 is selected to minimize a residualthickness layer (RTL) 112 (shown in FIGS. 1B and 1H) after imprinting.The RTL 112 is the total thickness 110 of the RDL 104 minus the depth124 of the imprint. In other words, the RTL 112 is the amount of thematerial of the RDL 104 remaining between the top of the substrate layer102 and the bottom of an imprinted via after being micro-imprinted witha stamp 108. In one embodiment, the thickness 110 of the RDL 104 isselected such that the RTL 112 is less than about 2 μm, such as lessthan 1 μm.

In one embodiment, the RDL 104 is a polyimide layer. The polyimide maybe an n-type photosensitive polyimide. In such an embodiment, thepolyimide layer may be deposited by a spin coating process, a spraycoating process, or a drop array pattern coating process. If thepolyimide layer is deposited using a spin coating process or a spraycoating process, the RDL 104 may be pre-baked after being deposited toevaporate a portion of solvent, which maximizes the imprint depth andminimizes pattern distortion due to the polyimide material hardening.Utilizing the spray coating process may enable the polyimide layer to beself-planarizing. If the polyimide layer is pre-baked, the polyimidematerial remains flowable and imprintable.

If the polyimide layer is deposited using a drop coating process, theRDL 104 may not be pre-baked after being deposited. When utilizing thedrop coating process, the polyimide may be deposited in a hatched arraypattern with controlled drop size and pitch. For example, the polyimidedrops may be deposited in a cross-hatched pattern having a diameterbetween about 440-500 μm and a pitch between about 500-800 μm. In oneembodiment, the drops had a diameter of about 450 μm and a pitch ofabout 570 μm. Utilizing the drop coating process may enable thepolyimide layer to be self-planarizing. Depositing the polyimide layerusing the drop coating process may result in minimal or no materialwaste.

In another embodiment, the RDL 104 is a flowable epoxy layer. Theflowable epoxy layer may be a flowable epoxy compound comprising silicaparticle fillers. The flowable epoxy layer may comprise one or morematerials that are flowable at a temperature range of about 90-180degrees Celsius and have a curing temperature of about 180 degrees orabove. In such an embodiment, the flowable epoxy layer is deposited by alamination process at a temperature of about 90-110 degrees Celsius. Ifthe flowable epoxy is utilized as the RDL 104, the RDL 104 may not bepre-baked after being deposited. In one embodiment, the substrate layer102 and the flowable epoxy layer are thermally matched using thecoefficient of thermal expansion (CTE).

FIG. 1B illustrates micro-imprinting the RDL 104 using a stamp 108 andsubstrate compression in the chamber 106, as performed in operation 204of method 200. The stamp 108 is applied to the RDL 104 with a pressureof about 1 bar or greater, resulting in the reverse tone image of thestamp pattern in the RDL 104 (i.e. the pillars of the stamp 108 creatingvias or holes in the RDL). The pressure is applied for about 1-2minutes. In one embodiment, the imprinting of the substrate 100 is donein a vacuum environment. The substrate 100 and/or the stamp 108 may beheated to about 50 to 100 degrees Celsius during the imprinting. The RDL104 is a flowable layer such that the RDL 104 conforms to the pattern ofthe stamp 108. The stamp 108 may comprise a UV transparent material. Inone embodiment, the stamp 108 is comprised of a UV transparent materialwhich allows UV wavelengths in the range of about 350-390 nm to passthrough the stamp 108. The stamp 108 may be comprised ofpolydimethylsiloxane (PDMS). The PDMS comprising stamp 108 enablesstiction-free stamp detachment and allows for solvent absorption.

In one embodiment utilizing a flowable epoxy layer as the RDL 104, theepoxy layer is laminated to the stamp 108, and the stamp 108 is thenattached to the substrate layer 102. The stamp 108 and RDL 104 are thenbrought to the flowable temperature range of the epoxy film. Theflowable temperature range of the epoxy film may be close to the curingtemperature of the epoxy film, such as between about 140-180 degreesCelsius.

FIG. 1C illustrates baking the RDL 104 imprinted with the stamp 108inside the chamber 106 by exposing the substrate 100 to heat 114, asperformed in operation 206 of method 200. The bake may be done at atemperature between about 80-200 degrees Celsius. For example, in anembodiment where polyimide is utilized as the RDL 104, the bake may bedone at a temperature between about 80-120 degrees Celsius for about30-60 minutes. Additionally, when polyimide is utilized as the RDL 104,the temperature and time of the in-chamber bake may be used to reduceand control the RTL 112. For example, baking the polyimide layer havinga thickness of about 6 μm at a temperature of about 100 degrees Celsiusfor about 2 minutes may reduce the RTL 112 from about 2 μm to about 0.5μm. In another embodiment where a flowable epoxy material is used as theRDL 104, the bake may be done at a temperature between about 180-200degrees Celsius for about 1-5 minutes. In such an embodiment where aflowable epoxy material is used, the baking temperature may be thecuring temperature.

FIG. 1D illustrates optionally UV curing the RDL 104 and the stamp 108by exposing the substrate 100 to UV light 116, as performed in operation208 of method 200. In one embodiment, the UV light 116 is applied forabout 2 minutes at a temperature between about 25-100 degrees Celsius.The UV curing may be done by applying a UV light 116 having a wavelengthbetween about 360-370 nm, such as 365 nm. In an embodiment where the RDL104 is comprised of a flowable epoxy material, the substrate 100 may notbe UV cured in operation 208, as the baking performed in operation 206may constitute the pre-cure processes. In such an embodiment, method 200proceeds directly from operation 206 to operation 210.

FIG. 1E illustrates removing the stamp 108 from the RDL 104, asperformed in operation 210 of method 200. The stamp 108 may be baked ina vacuum after being removed from the RDL 104 to remove any residualsolvent. In an embodiment where a flowable epoxy is utilized, the stamp108 may be demolded at a temperature of about 90-180 degrees Celsius.The RDL 104 may then be oven cured to freeze the plurality of vias 118formed from the micro-imprinted pattern, as performed in operation 212of method 200. Depending on the thickness 110 of the RDL 104 whendeposited and the stamp 108 used for imprinting, each via 118 may have adepth 124 between about 2-12 μm and a diameter 130 between about 0.5-50μm after being oven cured. In one embodiment, each via 118 has a depth124 less than about 8 μm and an RTL of less than about 1 μm after beingoven cured.

Moreover, if the RDL 104 is deposited to have a thickness of about 10μm, a stamp 108 having a pattern comprising of pillars having a diameterbetween about 5-50 μm and a height of about 10-12 μm may be used.Similarly, if the RDL 104 is deposited to have a thickness of about 5μm, a stamp 108 having a pattern comprising of pillars having a diameterbetween about 2-10 μm and a height of about 5-6 μm may be used. Thestamp 108 pillars may be designed such that the pillar height is thesame or up to 20% higher than that of the depth of the vias 118,allowing the vias to be formed with little to no excess residue. Forexample, if the RDL 104 is about 10 μm thick, a stamp 108 having apillar height of about 10-12 μm may be used. In an embodiment where aflowable epoxy layer is used as the RDL 104, the pillars of the stamp108 may be the same or taller than the thickness of the RDL 104.

FIGS. 1F-1I illustrates a close up view of a micro-imprinted via 118 ofFIG. 1E. FIG. 1F illustrates a side view of the via 118 having excessresidue 120 built up, according to one embodiment. FIG. 1G illustrates aperspective top view of the via 118 having excess residue 120, accordingto another embodiment. FIG. 1H illustrates a side view of the via 118having little to no excess residue. FIG. 1I illustrates a perspectivetop view of the via 118 having little to no excess residue. Excessresidue (i.e. extra built up RDL material) may accumulate in and aroundthe vias 118 due to heating the RDL 104. Depending on the materialselected for the RDL 104, excess residue may or may not build up. Forexample, in one embodiment, the vias 118 are only descummed and etchedwhen the RDL 104 comprises polyimide, and the vias 118 are not descummedwhen the RDL 104 comprises a flowable epoxy. However, if excess residueis accumulated when heating the flowable epoxy layer, the descum processmay be performed. If no excess residue is built up, the vias 118 neednot be descummed, and the vias 118 will have little to no excess residuefollowing the baking of operation 212, and method 200 ends at operation212. If the vias 118 have excess residue built up, a descumming processwill be performed to remove the excess residue, as performed inoperation 214 of method 200.

In operation 214, the micro-imprinted vias are optionally descummed toremove the excess built-up residue. The descumming process is performedwhile maintaining a temperature of about 0-20 degrees Celsius. To removethe residue, the substrate 100 may be etched with a 10:1 mixture ofoxygen (02) and tetrafluoro methane (CF₄) and then cooled using helium(He) or nitrogen (N₂). The substrate 100 may be etched and cooled one ormore times. For example, the substrate 100 may be etched and then cooledone to three times. Additionally, if the RTL 112 is equal to or lesserthan about 0.5 μm thick, the O₂/CF₄ etch and cooling processes may notbe performed at all. The substrate 100 may be etched with O₂/CF₄ forabout 10-40 seconds at an RF power of about 500-800 watts and a bias ofabout 50-100 watts. The N₂ or He cooling period may occur for about30-60 seconds. Following the one or more etching and cooling processes,a 4:2 mixture of argon (Ar) and hydrogen (H₂) may be used to clean andlevel off the rims 122 of the vias 118. The substrate 100 may be cleanedusing the Ar/H₂ mixture for about 40-60 seconds at an RF power of about800-1000 watts and a bias of about 100-200 watts.

Following the descumming process of operation 214, the rim 122 of thevia 118 may be tapered and smooth such that the surface of the rim 122is defined by a first angle θ₁ from the sidewall 128 of the via 118 anda second angle θ₂ from the surface 126 of the RDL 104, as shown in FIG.1H. Both the first and second angles θ₁, θ₂ may be greater than 90degrees (i.e. obtuse). The vias 118 may have an overall circular,cylindrical, or conical frustum shape. The vias 118 may have a largerdiameter at the surface 126 of the RDL 104 than the diameter at thebottom of the via 118 disposed adjacent to the RTL 112 and substratelayer 102. In other words, the sidewalls 128 of the vias 118 may beangled or tapered such that the vias 118 have a conical frustum shape.The RTL 112 of the vias 118 may be between 0-2 μm thick.

FIGS. 3A-3B illustrate various embodiments of stamp layouts 300, 350used for micro-imprinting. FIG. 3A illustrates one or more stamps306A-306C disposed in a multi-stamp layout 300 while FIG. 3B illustratesa plurality of stamps 356A-356C disposed in a full field stamp layout350. The stamps 306A-306C, 356A-356C may be the stamp 108 of FIGS.1A-1I, the RDL 304 may be the RDL 104 of FIGS. 1A-1I, and the substratelayer 302 may be the substrate layer 102 of FIGS. 1A-1I.

The stamps 306A-306C, 356A-356C may be comprised of a soft or hardmaterial, and may have a thickness between about 0.5-2 mm. The stamps306A-306C, 356A-356C may comprise a UV transparent material. In oneembodiment, the stamps 306A-306C, 356A-356C are comprised of a UVtransparent material which allows UV wavelengths in the range of about350-390 nm to pass through the stamps 306A-306C, 356A-356C. In oneembodiment, the stamps 306A-306C, 356A-356C are comprised of PDMS. ThePDMS comprising stamps 306A-306C, 356A-356C enable stiction-free stampdetachment and allow for solvent absorption. In one embodiment, thestamps 306A-306C, 356A-356C may have a pattern comprising of pillarshaving a diameter between about 8-12 μm spaced a distance of about 8-15μm apart. In another embodiment, the stamps 306A-306C, 356A-356C mayhave a pattern comprising of pillars having a diameter between about 4-6μm spaced a distance of about 3-10 μm apart.

In a multi-stamp layout 300 of FIG. 3A, one or more stamps 306A-306C areused to micro-imprint a RDL 304 disposed on a substrate layer 302. Eachstamp 306A-306C may be coupled to a separate backing 308A-308C. Thebackings 308A-308C may be glass backings. Utilizing a multi-stamp layout300 enables precise alignment when imprinting the RDL 304. One stamp306A may be used to imprint each portion of the panel or substrate 310individually, or a plurality of stamps 306A-306C may be used to imprintthe substrate 310 at once. For example, any number of stamps 306A-306Cmay be used, or as many as needed, to imprint the entire substrate 310at once, with each stamp 306A-306C being individually aligned with otherstamps 306A-306C and the substrate 310. The stamps 306A-306B may beapplied to the substrate 310 in a gradual way radially (i.e. center toedge), or linearly from one edge to the opposite edge (e.g. right toleft or left to right).

In the full field stamp layout 350 of FIG. 3B, a plurality of stamps356A-356C is coupled to a single backing 358. The backing 358 may be aglass backing. The plurality of stamps 356A-356C may be stitched to thebacking 358 with high accuracy to ensure precise alignment whenimprinting the panel or substrate 360. In such an embodiment, thebacking 358 is aligned with the substrate 360 such that each stamp356A-356B is in turn precisely aligned with the substrate 360. Thestamps 356A-356B may be applied to the substrate 360 in a gradual wayradially (i.e. center to edge), or linearly from one edge to theopposite edge (e.g. right to left/top to bottom or left to right/bottomto top).

FIGS. 4A-4B illustrate the in-chamber bake reducing and controlling theRTL 432 of a polyimide layer 430, according to one embodiment.Specifically, FIG. 4A illustrates micro-imprinting the polyimide layer430 using a stamp 408, such as shown in FIG. 1B and as described inoperation 204 above. FIG. 4B illustrates the substrate 400 after thesubstrate 400 and stamp 408 have been baked in the chamber, such asshown in FIG. 1C and as described in operation 206 above. The substrate400 may be the substrate 100 of FIGS. 1A-1I, the substrate layer 402 maybe the substrate layer 102 of FIGS. 1A-1I, the polyimide layer 430 maybe the RDL 104 of FIGS. 1A-1I, and the stamp 408 may be the stamp 108 ofFIGS. 1A-1I. Additionally, the micro-imprinting process may beaccomplished utilizing the method 200 of FIG. 2.

In FIGS. 4A-4B, the polyimide layer 430 is deposited on the substratelayer 402. The polyimide layer may have a thickness 440 of about 6 μm.The polyimide layer 430 may be deposited by the spin coating process,the spray coating process, or the drop array pattern coating processdescribed above in FIGS. 1A-1I.

As shown in FIG. 4A, the RTL 432 has a thickness 442 of about 2 μmimmediately after the polyimide layer 430 has been imprinted by thestamp 408. In FIG. 4B, the stamp 408 and the substrate 400 are baked inthe chamber at a temperature of about 100 degrees Celsius for about 2minutes. As such, the RTL 432 is reduced, now having a thickness 444 ofabout 0.5 μm. The substrate 400 and the stamp 408 may then be UV cured,such as in FIG. 1D above and as described in operation 208 above.

FIG. 5A illustrates a substrate 500 utilizing a flowable epoxy layer 550as the RDL being micro-imprinted by a stamp 508, according to oneembodiment. FIG. 5B illustrates a graph of time versus temperature formicro-imprinting a flowable epoxy layer 550. The substrate 500 comprisesa substrate layer 502, a flowable epoxy layer 550, and a stamp 508. Thesubstrate 500 may be the substrate 100, of FIGS. 1A-1I, the substratelayer 502 may be the substrate layer 102 of FIGS. 1A-1I, the flowableepoxy layer 550 may be the RDL 104 of FIGS. 1A-1I, and the stamp 508 maybe the stamp 108 of FIGS. 1A-1I. Furthermore, the substrate 500 may bemicro-imprinted using the method 200 of FIG. 2.

The flowable epoxy layer 550 may be a silica filled epoxy layer. Theflowable epoxy layer 550 may be micro-imprinted with the stamp 508 at atemperature near the cure temperature of the epoxy film, such as betweenabout 140-180 degrees Celsius. Once the stamp 508 is imprinted into theflowable epoxy layer 550, the substrate 500 and the stamp 508 may bebaked (e.g. pre-cured) in the chamber at a temperature of about 180-200degrees Celsius for about 1-5 minutes. The thickness 552 of the flowableepoxy layer 550 is less than the height 554 of the pillars of the stamp508. As such, the stamp 508 is in contact with the substrate layer 502,and no RTL 556 remains.

FIG. 5B illustrates a graph of time versus temperature formicro-imprinting a flowable epoxy layer 550. As shown in FIG. 5B, thestamp 508 is attached above the flowable temperature of the epoxy film550, near the curing temperature. The substrate 500 is then pre-cured ata temperature near the curing temperature. The stamp 508 is removed fromthe substrate 500 during a cooling period, when the temperature is belowthe curing temperature.

Utilizing the above described micro-imprinting and via formation methodallows a redistribution layer to be imprinted with a plurality of viashaving a maximized imprint depth and minimized pattern distortion. Forexample, the method permits a well-controlled via depth of less than 8μm and a residual thickness layer of less than 1 μm to be achieved.Furthermore, the micro-imprinting method does not utilize lithographyprocesses, and as such, expenses may be saved and less material may bewasted. Additionally, higher resolution patterning may be achieved sincethe method does not require optical resolution properties.

In one embodiment, a method of forming a plurality of vias in a panelcomprises depositing a polyimide layer on a substrate layer,micro-imprinting the polyimide layer with a stamp inside a chamber,baking the polyimide layer and the stamp inside the chamber, exposingthe polyimide layer and the stamp to UV light, removing the stamp fromthe polyimide layer to form a plurality of vias in the polyimide layer,performing an oven curing process on the polyimide layer, and descummingthe polyimide layer to remove excess residue.

The polyimide layer may be deposited using a spin coating process. Thepolyimide layer may be deposited using a spray coating process. Thepolyimide layer may be pre-baked prior to micro-imprinting. Baking thepolyimide layer and the stamp inside the chamber may reduce a residualthickness layer disposed between the stamp and the substrate layer.Descumming the polyimide layer may be performed at a temperature betweenabout 0 to 20 degrees Celsius. The descumming the polyimide layer maycomprise etching the excess residue one or more times, performing acooling process after each etch of the excess residue, and performing acleaning process. Oxygen and tetrafluoro methane may be used to etch theexcess residue. Helium or nitrogen may be used in the cooling process.Argon and hydrogen may be used in the cleaning process. A rim of each ofthe plurality of vias may be tapered following the cleaning process.

In another embodiment, a method of forming a plurality of vias in apanel comprises micro-imprinting a flowable epoxy layer with a stampinside a chamber, the flowable epoxy layer comprising silica particlefillers, baking the flowable epoxy layer and the stamp inside thechamber, and removing the stamp from the flowable epoxy layer to form aplurality of vias in the flowable epoxy layer.

The stamp may have a multi-stamp layout. The stamp may have a full fieldlayout. The method may further comprise exposing the flowable epoxylayer and the stamp to UV light prior to removing the stamp from theflowable epoxy layer and performing an oven curing process on theflowable epoxy layer after removing the stamp from the flowable epoxylayer. The flowable epoxy layer may comprise one or more materials thatare flowable at a temperature between about 90-180 degrees Celsius. Theflowable epoxy layer may be curable at a temperature greater than orequal to about 180 degrees Celsius. The flowable epoxy layer and thestamp may be baked inside the chamber at a temperature between about180-200 degrees Celsius for about 1-5 minutes.

The method may further comprise depositing the flowable epoxy layer on asubstrate layer prior to micro-imprinting the flowable epoxy layer. Theflowable epoxy layer may be deposited by lamination. Micro-imprintingthe flowable epoxy layer may comprises laminating the flowable epoxylayer on the stamp, attaching the stamp to a substrate layer, and bakingthe flowable epoxy layer and the stamp inside the chamber at atemperature between about 140-180 degrees Celsius. The stamp may beremoved from the flowable epoxy layer at a temperature between about140-180 degrees Celsius. The stamp may comprise a plurality of pillarshaving a height equal to or greater than a thickness of the flowableepoxy layer.

In yet another embodiment, a method of forming a plurality of vias in apanel comprises depositing a polyimide layer on a substrate layer usinga drop coat process, micro-imprinting the polyimide layer with a stampinside a chamber, baking the polyimide layer and the stamp inside thechamber, exposing the polyimide layer and the stamp to UV light,removing the stamp from the polyimide layer to form a plurality of viasin the polyimide layer, and performing an oven curing process on thepolyimide layer.

Depositing the polyimide layer on the substrate layer using a drop coatprocess may comprise depositing drops of polyimide on the substratelayer in a cross-hatched pattern with controlled drop size and pitch. Aresidual thickness layer may be disposed between a bottom of each of theplurality of vias and a top of the substrate layer. The residualthickness layer may have a thickness of less than about 1 μm.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A method of forming a plurality of vias in asubstrate, comprising: micro-imprinting a flowable epoxy layer with astamp inside a chamber, the flowable epoxy layer comprising silicaparticle fillers; baking the flowable epoxy layer and the stamp insidethe chamber; and removing the stamp from the flowable epoxy layer toform the plurality of vias in the flowable epoxy layer.
 2. The method ofclaim 1, wherein the stamp has a multi-stamp layout or a full fieldlayout.
 3. The method of claim 1, further comprising: exposing theflowable epoxy layer and the stamp to UV light prior to removing thestamp from the flowable epoxy layer; and performing an oven curingprocess on the flowable epoxy layer after removing the stamp from theflowable epoxy layer.
 4. The method of claim 1, wherein the flowableepoxy layer comprises one or more materials that are flowable at atemperature between about 90-180 degrees Celsius, and wherein theflowable epoxy layer is curable at a temperature greater than or equalto about 180 degrees Celsius.
 5. The method of claim 1, wherein theflowable epoxy layer and the stamp are baked inside the chamber at atemperature between about 180-200 degrees Celsius for about 1-5 minutes.6. The method of claim 1, further comprising depositing the flowableepoxy layer on a substrate layer prior to micro-imprinting the flowableepoxy layer, wherein the flowable epoxy layer is deposited bylamination.
 7. The method of claim 1, wherein micro-imprinting theflowable epoxy layer comprises: laminating the flowable epoxy layer onthe stamp; attaching the stamp to a substrate layer; and baking theflowable epoxy layer and the stamp inside the chamber at a temperaturebetween about 140-180 degrees Celsius.
 8. The method of claim 1, whereinthe stamp is removed from the flowable epoxy layer at a temperaturebetween about 140-180 degrees Celsius.
 9. The method of claim 1, whereinthe stamp comprises a plurality of pillars having a height equal to orgreater than a thickness of the flowable epoxy layer.
 10. A method offorming a plurality of vias in a substrate, comprising: depositing apolyimide layer on a substrate layer; pre-baking the polyimide layer;micro-imprinting the polyimide layer with a stamp inside a chamber;baking the polyimide layer and the stamp inside the chamber; exposingthe polyimide layer and the stamp to a UV light curing process; removingthe stamp from the polyimide layer to form the plurality of vias in thepolyimide layer; performing an oven curing process on the polyimidelayer; and descumming the polyimide layer to remove excess residue. 11.The method of claim 10, wherein the polyimide layer is deposited using aspin coating process or a spray coating process.
 12. The method of claim10, wherein the pre-baking the polyimide layer is performed at atemperature between about 75 to 90 degrees Celsius.
 13. The method ofclaim 10, wherein micro-imprinting the polyimide layer is performed at apressure of about 1 bar or greater.
 14. The method of claim 13, whereinmicro-imprinting the polyimide layer is performed at a temperaturebetween about 50 degrees to 100 degrees Celsius.
 15. The method of claim10, wherein baking the polyimide layer is performed at a temperaturebetween about 80 degrees to 200 degrees Celsius.
 16. The method of claim10, wherein exposing the polyimide layer and the stamp to a UV lightcuring process comprises exposing the polyimide layer and the stamp toUV light having a wavelength between about 360 to 370 nm, and atemperature between about 25 to 100 degrees Celsius.
 17. The method ofclaim 10, wherein descumming the polyimide layer is performed at atemperature between about 0 to 20 degrees Celsius.
 18. The method ofclaim 17, wherein the descumming the polyimide layer comprises: etchingthe excess residue one or more times; performing a cooling process aftereach etch of the excess residue; and performing a cleaning process. 19.A method of forming a plurality of vias in a substrate, comprising:depositing a polyimide layer on a substrate layer via a spray coating orspin coating process; pre-baking the polyimide layer at a temperaturebetween about 75 to 90 degrees Celsius; micro-imprinting the polyimidelayer with a transparent stamp inside a chamber; baking the polyimidelayer and the transparent stamp inside the chamber at a temperaturebetween about 80 degrees to 200 degrees Celsius; exposing the polyimidelayer and the transparent stamp to a UV light curing process; removingthe transparent stamp from the polyimide layer to form the plurality ofvias in the polyimide layer; performing an oven curing process on thepolyimide layer; and descumming the polyimide layer at a temperaturebetween about 0 to 20 degrees Celsius to remove excess residue.
 20. Themethod of claim 10, wherein micro-imprinting the polyimide layer isperformed at a pressure of about 1 bar or greater and at a temperaturebetween about 50 degrees to 100 degrees Celsius.